august 2000 dsc-2946/8 1 ?2000 integrated device technology, inc. not recommended for new designs features u u u u u high-speed address/chip select time C military: 25/35/45/55/70/85/100ns (max.) C industrial: 25/35ns (max.) C commercial: 20/25/35ns (max.) low power only u u u u u low-power operation u u u u u battery backup operation C 2v data retention u u u u u produced with advanced high-performance cmos technology u u u u u input and output directly ttl-compatible u u u u u available in standard 28-pin (300 or 600 mil) ceramic dip, 28-pin (600 mil) plastic dip, 28-pin (300 mil) soj and 32-pin lcc u u u u u military product compliant to mil-std-883, class b functional block diagram description the idt 71256 is a 262,144-bit high-speed static ram organized as 32k x 8. it is fabricated using idt's high-performance, high-reliability cmos technology. address access times as fast as 20ns are available with power consumption of only 350mw (typ.). the circuit also offers a reduced power standby mode. when cs goes high, the circuit will automatically go to and remain in, a low-power standby mode as long as cs remains high. in the full standby mode, the low-power device consumes less than 15 m w, typically. this capability provides significant system level power and cooling savings. the low-power (l) version also offers a battery backup data retention capability where the circuit typically consumes only 5 m w when operating off a 2v battery. the idt71256 is packaged in a 28-pin (300 or 600 mil) ceramic dip, a 28-pin 300 mil soj, a 28-pin (600 mil) plastic dip, and a 32-pin lcc providing high board level packing densities. the idt71256 military ram is manufactured in compliance with the latest revision of mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. cmos static ram 256k (32k x 8-bit) idt71256s idt71256l a 0 address decoder 262,144 bit memory array i/o control 2946 drw 01 input data circuit we cs v cc gnd a 14 i/o 0 i/o 7 control circuit oe ,
2 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges not recommended for new designs absolute maximum ratings (1) pin configurations dip/soj top view truth table (1) 32-pin lcc top view 2946 drw 02 5 6 7 8 9 10 11 12 gnd 1 2 3 4 24 23 22 21 20 19 18 17 d28-3 p28-1 d28-1 so28-5 13 14 28 27 26 25 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v cc a 14 we a 13 a 8 a 10 a 11 oe a 12 cs i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 a 9 16 15 5 6 7 8 9 l32-1 20 19 18 17 10 11 12 13 1 v 16 15 2946 drw 03 14 4 a 3 a 1 , 1 index 2 21 22 23 24 25 26 27 28 29 32 31 30 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 a 9 a 11 nc oe a 10 cs i/o 7 i/o 8 a 7 a 12 a 14 n c v c c w e a 13 i/o 1 i/o 2 g n d n c i/o 3 i/o 4 i/o 5 , pin descriptions name description a 0 - a 14 address inputs i/o 0 - i/o 7 data input/output cs chip select we write enable oe output enable gnd ground v cc power 29 46 tb l 01 capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is determined by device characterization, but is not production tested. note: 1. h = v ih , l = v il , x = don't care. we cs oe i/o function xhxhigh-z standby (i sb ) xv hc xhigh-z standby (i sb1 ) h l h high-z output disabled hlld out read data llxd in write data 29 46 tb l 02 note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol rating com'l. ind. mil. unit v te rm terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 v t a operating temperature 0 to +70 -40 to +85 -55 to +125 o c t bias temperature under bias -55 to +125 -55 to +125 -65 to +135 o c t stg storage temperature -55 to +125 -55 to +125 -65 to +150 o c p t power dissipation 1.0 1.0 1.0 w i out dc output current 50 50 50 ma 2946 tbl 03 symbol parameter (1) conditions max. unit c in input capacitance v in = 0v 11 pf c i/o i/o capacitance v out = 0v 11 pf 2946 tbl 04
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 3 not recommended for new designs recommended operating temperature and supply voltage recommended dc operating conditions note: 1. v il (min.) = C3.0v for pulse width less than 20ns, once per cycle. grade temperature gnd vcc military -55 o c to +125 o c0v 5v 10% industrial -40 o c to +85 o c0v 5v 10% commercial 0 o c to +70 o c0v 5v 10% 29 46 tb l 05 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 v v il input low voltage -0.5 (1 ) ____ 0.8 v 2 946 tbl 06 dc electrical characteristics (1,2) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) 71256s/l20 71256s/l25 71256s/l35 71256s/l45 symbol parameter power com'l. mil. com'l & ind mil. com'l. & ind mil. com'l. mil. unit i cc dynamic operating current cs < v il , outputs open v cc = max., f max (2) s ____ ____ ____ 150 ____ 140 ____ 135 ma l135 ____ 115 130 105 120 ____ 115 i sb standby power supply current (ttl le v e l), cs > v ih , v cc = max., outputs open, f = f max (2) s ____ ____ ____ 20 ____ 20 ____ 20 ma l3 ____ 3333 ____ 3 i sb1 full standby power supply current (cmos level), cs > v hc , v cc = max., f = 0 s ____ ____ ____ 20 ____ 20 ____ 20 ma l0.4 ____ 0.4 1.5 0.4 1.5 ____ 1.5 2946 tbl 07 71256s/l55 71256s/l70 71256s/l85 71256s/l100 symbol parameter power mil. mil. mil. mil. unit i cc dynamic operating current cs < v il , outputs open v cc = max., f max (2) s 135 135 135 135 ma l 115 115 115 115 i sb standby power supply current (ttl le ve l), cs > v ih , v cc = max., outputs open, f = f max (2) s20202020 ma l3333 i sb1 full standby power supply current (cmos level), cs > v hc , v cc = max., f = 0 s20202020 ma l 1.5 1.5 1.5 1.5 2946 tbl 08 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , all address inputs are cycling at f max ; f = 0 means no address pins are cycling.
4 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges not recommended for new designs ac test conditions *includes scope and jig capacitances figure 2. ac test load (for t clz , t olz , t chz, t ohz , t ow , and t whz ) figure 1. ac test load input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 5ns 1.5v 1.5v see figures 1 and 2 29 46 tb l 09 2946 drw 04 480 w 255 w 30pf* data out 5v , 2946 drw 05 480 w 255 w 5pf* data out 5v , dc electrical characteristics (v cc = 5.0v 10%) data retention characteristics over all temperature ranges (l version only) (v lc = 0.2v, v hc = v cc - 0.2v) notes: 1. t a = +25c. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter test conditions idt71256s idt71256l unit min. typ. max. min. typ. max. |i li | input leakage current v cc = max., v in = gnd to v cc mil. com"l & ind. ____ ____ ____ ____ 10 5 ____ ____ ____ ____ 5 2 a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc mil. com"l & ind. ____ ____ ____ ____ 10 5 ____ ____ ____ ____ 5 2 a v ol output low voltage i ol = 8ma, v cc = min. ____ ____ 0.4 ____ ____ 0.4 v i ol = 10ma, v cc = min. ____ ____ 0.5 ____ ____ 0.5 v oh output high voltage i oh = -4ma, v cc = min. 2.4 ____ ____ 2.4 ____ ____ v 2946 tbl 10 typ. (1) v cc @ max. v cc @ symbol parameter test condition min. 2.0v 3.0v 2.0v 3.0v unit v dr v cc for data retention ____ 2.0 ____ ____ ____ ____ v i ccdr data retention current mil. com'l. & ind. ____ ____ ____ ____ ____ ____ 500 120 800 200 m a t cdr chip deselect to data retention time cs > v hc 0 ____ ____ ____ ____ ns t r (3) operation recovery time t rc (2) ____ ____ ____ ____ ns 294 6 tb l 11
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 5 not recommended for new designs ac electrical characteristics (v cc = 5.0v 10%, all temperature ranges) low v cc data retention waveform 2946 drw 06 data retention mode 4.5v 4.5v v dr 3 2v v ih v ih t r t cdr v cc cs v dr notes: 1. 0 to +70c temperature range only. 2. this parameter is guaranteed by device characterization, but is not production tested. 3. C55c to +125c temperature range only. symbol parameter 71256l20 (1) 71256s25 71256l25 71256s35 71256l35 71256s45 (3) 71256l45 (3) unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 20 ____ 25 ____ 35 ____ 45 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ____ 45 ns t acs chip select access time ____ 20 ____ 25 ____ 35 ____ 45 ns t cl z (2) chip sel ect to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t chz (2) chip desele ct to output in high-z ____ 10 ____ 11 ____ 15 ____ 20 ns t oe output enable to output valid ____ 10 ____ 11 ____ 15 ____ 20 ns t ol z (2) output enab le to output in low-z 2 ____ 2 ____ 2 ____ 0 ____ ns t ohz (2) output disab le to output in high-z 2 8 2 10 2 15 ____ 20 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ ns wri te cycl e t wc write cycle time 20 ____ 25 ____ 35 ____ 45 ____ ns t cw chip select to end-of-write 15 ____ 20 ____ 30 ____ 40 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ 40 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 15 ____ 20 ____ 30 ____ 35 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data to write time overlap 11 ____ 13 ____ 15 ____ 20 ____ ns t whz (2) write enab le to output in high-z ____ 10 ____ 11 ____ 15 ____ 20 ns t dh data hold from write time 0 ____ 0 ____ 0 ____ 0 ____ ns t ow (2) output active from end-of-write 5 ____ 5 ____ 5 ____ 5 ____ ns 29 46 tb l 12
6 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges not recommended for new designs ac electrical characteristics (v cc = 5.0v 10%, military temperature ranges) notes: 1. -55 to +125c temperature range only. 2. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter 71256s55 (1) 71256l55 (1) 71256s70 (1) 71256l70 (1) 71256s85 (1) 71256l85 (1) 71256s100 (1) 71256l100 (1) unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 55 ____ 70 ____ 85 ____ 100 ____ ns t aa address access time ____ 55 ____ 70 ____ 85 ____ 100 ns t acs chip select access time ____ 55 ____ 70 ____ 85 ____ 100 ns t cl z (2) chip sel ect to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t chz (2) chip desele ct to output in high-z ____ 25 ____ 30 ____ 35 ____ 40 ns t oe output enable to output valid ____ 25 ____ 30 ____ 35 ____ 40 ns t ol z (2) output enab le to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t ohz (2) output disab le to output in high-z 0 25 0 30 ____ 35 ____ 40 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ ns wri te cycl e t wc write cycle time 55 ____ 70 ____ 85 ____ 100 ____ ns t cw chip select to end-of-write 50 ____ 60 ____ 70 ____ 80 ____ ns t aw address valid to end-of-write 50 ____ 60 ____ 70 ____ 80 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 40 ____ 45 ____ 50 ____ 55 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data to write time overlap 25 ____ 30 ____ 35 ____ 40 ____ ns t whz (2) write enab le to output in high-z ____ 25 ____ 30 ____ 35 ____ 40 ns t dh data hold from write time ( we )0 ____ 0 ____ 0 ____ 0 ____ ns t ow (2) output active from end-of-write 5 ____ 5 ____ 5 ____ 5 ____ ns 29 46 tb l 13
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 7 not recommended for new designs timing waveform of read cycle no. 2 (1,2,4) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. address valid prior to or coincident with cs transition low. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 1 (1) address cs oe data out t rc t aa t oh t oe t acs t clz (5) t olz (5) 2946 drw 07 t chz (5) t ohz (5) 2946 drw 08 address data out t rc t aa t oh t oh , timing waveform of read cycle no. 2 (1,3,4) cs data out t acs t clz (5) 2946 drw 09 t chz (5)
8 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges not recommended for new designs timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4,6) notes: 1. a write occurs during the overlap of a low cs and a low we . 2. t wr is measured from the earlier of cs or we going high to the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals must not be applied. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. 6. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz +t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short as the specified t wp . for a cs controlled write cycle, oe may be low with no degradation to t cw . timing waveform of write cycle no. 2 ( cs controlled timing) (1,2,4) cs 2946 drw 10 t aw t wr t dw data in address t wc we t wp t dh data out t wz t t as (5) (3) oe (3) (6) ow t ohz (5) t wr cs 2946 drw 11 t aw t dw data in address t wc we t cw t dh2 as t t (6)
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 9 not recommended for new designs ordering information ? commercial & industrial ordering information ? military x power speed xxx package x process/ temperature range b military (C55c to +125c) compliant to mil-std-883, class b td d l32 300 mil cerdip (d28-3) 600 mil cerdip (d28-1) leadless chip carrier (32-pin) (l32-1) 25 35 45 55 70 85 100 s l standard power low power device type 71256 idt speed in nanoseconds 2946 drw 12 xxx x power xx speed xxx package x process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) y p 300 mil soj (so28-5) 600 mil plastic dip (p28-1) 20 25 35 l low power only device type 71256 idt speed in nanosecond s 2946 drw 13 , 300 mil soj only, commercial only
10 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges not recommended for new designs datasheet document history 11/4/99 updated to new format pp. 1C5, 9 added industrial temperature range offerings pg. 1 removed 30, 120, and 150ns military and 45ns commercial speed grade offerings. pg. 2 removed p28-2 package from dip/soj top view pg. 3 removed 30ns and 45ns (commercial only) speed grade offerings from dc electrical table revised notes and footnotes pg. 5 removed 30ns speed grade offering from ac electrical table revised notes and footnotes pg. 6 expressed military temperature range on ac electrical table revised notes and footnotes pg. 8 removed note 1 and renumbered notes and footnotes pg. 9 revised ordering information and presented by temperature range offering pg. 10 added datasheet document history 08/09/00 not recommended for new designs corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax:408-492-8674 800 544-7726, x4033 www.idt.com the idt logo is a registered trademark of integrated device technology, inc.
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